CODEWITHSUNDEEP
riscv
Thomas Peyret
Thomas Peyret

Reputation: 23

32 bit Datapath RISCV core

I'm trying to parametrize the rocket core by changing the configuration in PublicConfig.scala.

However, when I change XprLen and L1D_SETS to 32, I have a compilation problem.

What is the proper way to genarate a 32 bit data path with the Rocket Chip Generator, if possible?

Upvotes: 2

Views: 402

Answers (1)

Chris
Chris

Reputation: 3987

The Rocket-chip does not currently support generating a 32b processor.

While the required changes to the datapath would be minimal, the host-target interface for communicating to the front-end server (as Rocket currently only runs in a tethered mode) has only been spec'ed out for 64b cores.

ALso, L1D_SETS is the number of "sets" in the L1 data-cache (such that L1D_WAYS * L1D_SETS * 64 bytes per line is the total cache capacity in bytes).

Upvotes: 1

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