CODEWITHSUNDEEP
if-statementverilog
Farhood
Farhood

Reputation: 391

How to use if statements in verilog

I'm a total disaster at using verilog for implementing but this issue is walking on my nerves around an hour and I can't fix it!

here's my code 

genvar i;
assign eq=1; 
assign gr=0;
generate for(i=7 ; i>=0 ; i=i-1)
        initial begin
        if(eq&&~gr)
            if (a[i]&~b[i])
              initial begin
               assign gr=1;
               assign eq=0;
              end
            else if (~a[i]|b[i])
            initial begin
              assign gr=0;

    assign eq=0;
    end
    end
endgenerate

the idea was to create some if statements so I could compare a[i] and b[i] if gr was 0 and eq was 1. the algorithm cannot be changed cause it's an assignment and I have to work this way but I'm really eager to find where the problem is (verilog's error description is not helping at all)

Upvotes: 0

Views: 15662

Answers (1)

Greg
Greg

Reputation: 19096

  • generate blocks are used to replicate hardware at compile/elaboration time
  • initial blocks only run one at time 0. Changes to a and b will have no effect. It is illegal to nest initial blocks.
  • assign statements should not be used in initial blocks (it is legal but highly discouraged and is in consideration for depreciation). Generally a non-tri-state assign to a net should be done only once.
  • For continuous evaluation you need to use an always block

Best guess, this is the functionality you intended:

integer i;
reg eq,gr; 

always @* begin
  for (i=7 ; i>=0 ; i=i-1) begin
    if (eq&&~gr) begin
      if (a[i]&~b[i]) begin
        gr=1;
        eq=0;
      end
      else if (~a[i]|b[i]) begin
        gr=0;
      end
    end
    eq=0;
  end
end

Upvotes: 1

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