CODEWITHSUNDEEP
optimizationverilogfpgaxilinxxilinx-ise
Luis Filipe Martins Barros
Luis Filipe Martins Barros

Reputation: 167

Advanced verilog design analysis

I'm trying to implement a design into a Virtex II Pro FPGA (from Xilinx). The problem is the design is overmapped, taking up too many resources. To overcome that, I needed to know which blocks of my code are the most demanding (require more resources - LUTs, FFs, Slices, etc). By that I mean: How many resources is this if-else ( or switch-case, while, etc) requiring?

Xilinx doesn't have a tool for this purpose. Is there a workaround? Or, even better, is there a 3rd party tool capable of doing this?

Since my FPGA is quite old, I'm using ISE and PlanAhead 10.1.

Upvotes: 1

Views: 311

Answers (3)

mbschenkel
mbschenkel

Reputation: 1905

You can also use the Xilinx tool PlanAhead which is not really intended for this, but gives a nice, hierarchical breakdown with information on resource usage for any block on any hierarchy level. I can only provide an obfuscated screenshot at the moment, but it should give you an idea of what to expect.

PlanAhead screenshot

PlanAhead can be opened from within Xilinx through Tools > PlanAhead > "Floorplan Area/...".

Upvotes: 1

Amir
Amir

Reputation: 507

If we have one module to synthesize, I think there is no way to see which hardware is related to a specific if or case statement, because synthesis tools synthesize all the code together.(for example sometimes 2 or 3 processes in your vhdl code is synthesized to a specific hardware). Actually according to the synthesis options and constrains it guess that what hardware could be generated.

However if you want to see the resources usage of each module (not each if statement) you can see the Synthesis Report on "ISE -> project -> Design summary". If you synthesized your code without any errors Synthesis Report tell you how many resources (LUT, FF, IO, Buffer, ..) is used.

Upvotes: 1

Jonathan Drolet
Jonathan Drolet

Reputation: 3388

I had to use ISE 10.1 recently after a long hiatus. I don't remember what would be the better solution, but this worked for me:

  • In the synthesis option, set the option "Netlist Hierarchy" to "Rebuilt".
  • Start the process "Implement Design" -> "Translate" -> "Floorplan design"

You should see be able to navigate your hierarchy and see the resources usage of the sub-modules.

Upvotes: 1

Related Questions