CODEWITHSUNDEEP
verilogfpga
Shivam Lakhotia
Shivam Lakhotia

Reputation: 93

Xilinx: Common synthesis Warnings

module InstructionRegister(ir_in,ir_out,ir_r_enable,ir_w_enable,clock);
    input clock;
    input [7:0] ir_in;
    output reg [7:0] ir_out;
    input ir_w_enable;
    input ir_r_enable;
    reg [7:0] insreg;
    initial
    begin
        ir_out=8'b0;
    end
    always @(posedge clock)
        begin
            if(ir_w_enable)
                insreg <= ir_in;
            else if(ir_r_enable)
                ir_out <= insreg;
        end
endmodule

Warning:Due to constant pushing, FF/Latch is unconnected in block (for all 8 bits)

Now, I searched for the warning and the most common explanation was value of register is not changing but here the value depends on the input which may vary...so why this warning?

Upvotes: 0

Views: 504

Answers (1)

mcleod_ideafix
mcleod_ideafix

Reputation: 11418

Your module defintely is not the cause of this warning. It's one (or more) of the signals that go to this module from the module that instantiates it.

"Constant pushing" means that the ir_in bus is connected to is a constant value, so the register always store the same value, hence the synthesizer optimizes the module throwing away the register.

This is something that usually happens when a module is being tested and, for commodity reasons, you connect inputs to a constant value.

Upvotes: 1

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