CODEWITHSUNDEEP
verilog
user4615534
user4615534

Reputation: 55

strange thing in concatenation verilog

I have a module in verilog which gets two 64-bit numbers. These numbers are random. The strange thing is that when I debug it, fa is correct and starts with 1, but fb unexpectedly starts with 0.

What is wrong with it?

module adder(sum,a, b);
   input [63:0]   a;
   input [63:0] b;
   reg one;
output  reg [63:0] sum;
   reg [63:0] fa,fb;

    always @(a or b) begin
      one=1'b1;
    
      fb={one,b[51:0],12'b0};
      fa={one,a[51:0],12'b0};
      sum=64'b1;
    end
  endmodule

Upvotes: 1

Views: 711

Answers (1)

toolic
toolic

Reputation: 62037

There is a bit width mismatch in this assignment:

fb={one,b[51:0],12'b0};

The left-hand side (LHS) is 64 bits wide, but the right-hand side (RHS) is 65 bits wide.

LHS:

  • fb is 64 bits wide [63:0].

RHS:

  • one is 1 bit wide
  • b[51:0] is 52 bits wide
  • 12'b0 is 12 bits wide

(1+52+12=65)

one is ignored because fb[11:0]=12'b0 and fb[63:12]=b[51:0]. Therefore, if b[51]=0, then fb[63]=0.

The same is true for fa.

Upvotes: 3

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