CODEWITHSUNDEEP
verilog
user3857154
user3857154

Reputation: 38

I'm getting an expecting 'endmodule' error in Verilog

I've looked over my code, and I see nothing wrong. Here's the specific error, any help appreciated: ERROR:HDLCompilers:26 - "myGates.v" line 33 expecting 'endmodule', found 'input' Analysis of file <"myGates.prj"> failed.

module myGates(
    input sw0,
    input sw1,
    input sw2,
    input sw3,
    output ld0, 
     output ld1, 
     output ld2, 
     output ld3, 
     output ld7
    );

     input sw0, sw1, sw2, sw3;
     output ld0, ld1, ld2, ld3, ld7;
     wire w1, w2;

     assign ld0 = sw0;
     assign ld1 = sw1;
     assign ld2 = sw2;
     assign ld3 = sw3;

     and u1 (w1, sw0, sw1);
     and u2 (w2, sw2, sw3);
     and u3 (ld7, w1, w2);
endmodule

Upvotes: 0

Views: 2788

Answers (1)

Greg
Greg

Reputation: 19094

You are mixing ANSI and non-ANSI header styles. You have to pick one

ANSI : Supported since IEEE std 1364-2001 (RECOMMENDED): 

module myGates( // direction, type, range, and name here
    input sw0, sw1, sw2, sw3, 
    output ld0, ld1, ld2, ld3, 
    output ld7
  );

  wire w1, w2; // internal wire/reg

  // your code ...
endmodule

Non-ANSI : Mandated in IEEE std 1364-1995 and pre-IEEE. Since IEEE std 1364-2001 this is supported for backward comparability.

module myGates( // name only here
    sw0, sw1, sw2, sw3, 
    ld0, ld1, ld2, ld3, 
    ld7
  );

  input sw0, sw1, sw2, sw3; // direction & range here
  output ld0, ld1, ld2, ld3;
  output ld7;
  // <- if 'reg' type, then type & range here 

  wire w1, w2; // internal wire/reg

  // your code ...
endmodule

Upvotes: 2

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