schemacs
schemacs

Reputation: 2891

Makefile for compiling each c source file into a Linux kernel module

I have a directory full of c source files, each one could be compiled into a independent kernel module, the following Makefile doesn't work:

sources := $(wildcard *.c)
obj-m += $(patsubst %.c,%.o,$(sources))

all:
    make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

clean:
    make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean 

But if I use obj-m += mod1.o mod2.o this will work.

Upvotes: 2

Views: 354

Answers (2)

Santosh A
Santosh A

Reputation: 5361

You can use the below snippet from makefile

obj-m += $(subst .c,.o, $(wildcard *.c))

subst will replace .c suffixes with .o

Upvotes: 1

Jonsmoke
Jonsmoke

Reputation: 850

try to use something like :

obj-m += $(sources:.c=.o)

Upvotes: 0

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