CODEWITHSUNDEEP
verilogxilinx-ise
Amir
Amir

Reputation: 507

Sensitivity list error

I want to compute sum of elements of an array. Elements of the array are assigned on each clock rising edge (sequentially). I don't want to get the sum of elements on the next clock rising edge, So the design of sum must be combinational. I can get the correct result in simulation without any errors, but my code is not synthesized in ISE (Xilinx Synthesis tool). I'm working on Spartan3.

My code :

always @* begin
    sum = 0;
    for (i=0; i<K; i=i+1)
        sum = sum + shiftReg[i];    
end

ERROR :

Xst:902 - Unexpected shiftReg event in always block sensitivity list.

I searched for solutions. One way is to add all of the elements of shiftReg in sensitivity list, but in my project the number of elements is K (K is a parameter).

Upvotes: 2

Views: 2681

Answers (1)

mcleod_ideafix
mcleod_ideafix

Reputation: 11418

I'm afraid it's a limitation of the XST synthesizer. The very same solution you provide states that this issue has been solved for Virtex 6 and Spartan 6 devices, so it must be some kind of limitation regarding resources in the Spartan 3, or, more probably, a bit of lazyness from Xilinx engineers.

I've tested this example module:

module addall (
  input wire clk,
  input wire [3:0] addr,
  input wire load,
  input wire [7:0] din,
  output reg [7:0] tot
);

  reg [7:0] sr[0:15];
  always @(posedge clk) begin
    if (load)
      sr[addr] <= din;
  end

  integer i;
  always @* begin
    tot = 8'h00;
    for (i=0;i<=15;i=i+1)
        tot = tot + sr[i];
  end
endmodule

It synthesizes well on Icarus Verilog + YOSIS 0.3.0 http://www.edaplayground.com/x/5q9

It synthesizes well in XST 12.4 using a Spartan 6 device

It gives me the same error as you with the same XST version, if I change to Spartan 3E.

Possible workaround: use Icarus Verilog with target vhdl to convert the offending module into VHDL and add it to your design instead of the original Verilog module.

Upvotes: 5

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