CODEWITHSUNDEEP
interfaceverilogiverilog
adrianX
adrianX

Reputation: 627

How do i get the input and output names of Verilog module using scripts or tools?

is there a tool or script somewhere that allows me to parse Verilog files to obtain the names of the inputs and outputs of the module? i tried to look at iverilog and yosys but they do not seem to have this feature. i can write my own but i do not want to reinvent the wheel. thanks!

Upvotes: -1

Views: 1783

Answers (2)

dave_59
dave_59

Reputation: 42723

Tools like ModelSim/Questa has a Tcl command find -ports that does this for you. You can also use the Verilog VPI, but not with the free version of ModelSim.

Upvotes: 1

toolic
toolic

Reputation: 62192

Verilog-Perl can parse Verilog to obtain the names of the inputs and outputs of the module. It is free software which can be downloaded and installed. There are many code examples to do what you want, but it does require some knowledge of the Perl language. You are wise to not want to reinvent this wheel.

Upvotes: 1

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