CODEWITHSUNDEEP
verilogsystem-verilog
VIJETH ANCHATGERI
VIJETH ANCHATGERI

Reputation: 73

SystemVerilog port kind [net or variable]?

I need a clarification on SystemVerilog IEEE Std 1800-2012, ports section 23.2.2.3.

The LRM says when the port kind (net type or variable) is omitted on input port, it defaults to net type, but when the input port is of bit data type without specifying the port kind, does it infer to net type according to LRM?

A reply would be highly appreciated!

Upvotes: 4

Views: 2529

Answers (2)

Jonathan Mayer
Jonathan Mayer

Reputation: 1482

"bit" only specifies the data type, not the net type, of a signal.

When you declare a port as "input bit foo", the tools are supposed to infer net type based on whatever `default_nettype is set to.

A number of verilog style guides have recommended "`default_nettype none" as a poor-mans linting tool to detect typos in net names. This breaks under systemverilog, in so far as it then starts requiring that everything be declared with both a net and a data type, like this:

input wire bit foo

Everybody hates that, so instead:

  • don't use "`default_nettype none"
  • use a real linting tool to do linting instead.

Upvotes: 1

dave_59
dave_59

Reputation: 42616

The port kind defaults to a net and you referenced, but 6.7.1 Net declarations with built-in net types says that net types are restricted to 4-state integral types. So you should get an error if you try to declare input bit instead of input var bit.

Note that earlier versions of the SystemVerilog LRM had the default port kind a variable when specifying a data type without a port kind. Some tools might not generate an error if they are not up to date.

Upvotes: 3

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