CODEWITHSUNDEEP
assemblycpu-registerscpu-architecturemachine-codelc3
committedandroider
committedandroider

Reputation: 9301

Shouldn't R3 hold address x3307?

I am doing a practice question from Question 7 enter image description here

Shouldn't the address I highlighted be x3307, not x3308?

The way I reasoned this out was that (PC before 2nd instruction) = (PC after 1st instruction).

The PC after 1st instruction is x3301. Therefore when the second instruction executes, the PC, x3301 will be incremented by 6 to x3307.

Does everyone agree? Or did I miss something and R3 should actually store x3308?

Upvotes: 0

Views: 42

Answers (2)

Michael Burr
Michael Burr

Reputation: 340426

From Appendix A of Patt & Patel, the notational conventions (Table A.1) says this about the PC:

Program Counter; 16-bit register that contains the memory address of the next instruction to be fetched. For example, during execution of the instruction at address A, the PC contains address A + 1, indicating the next instruction is contained in A + 1.

the specification for the LEA opcode says:

An address is computed by sign-extending bits [8:0] to 16 bits and adding this value to the incremented PC.

So when the second instruction is being executed the 'incremented PC' is 0x3302. Adding 6 to that results in 0x3308.

Upvotes: 0

Jester
Jester

Reputation: 58802

PC-relative offsets are applied on top of the already incremented PC, that is the "after" value of the PC, or in other words, the address of the following instruction.

Upvotes: 2

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