CODEWITHSUNDEEP
exceptionarmcpu-registersarm64
crazzy
crazzy

Reputation: 169

No LR and SPSR for EL0 in Aarch64

In AArch64, There are 4 exception levels viz EL0-3. ARM site mentions there are 4 Stack pointers (SP_EL0/1/2/3) but only 3 exception Link registers (ELR_EL1/2/3) and only 3 saved program status register(SPSR_EL1/2/3).

Why the ELR_EL0 and SPSR_EL0 are not required?

P.S. Sorry if this is a silly question. I am new to ARM architecture.

Upvotes: 1

Views: 921

Answers (1)

Notlikethat
Notlikethat

Reputation: 20924

By design exceptions cannnot target EL0, so if it can't ever take an exception then it has no use for the machinery to be able to return from one.

To expand on the reasoning a bit (glossing over the optional and more special-purpose higher exception levels), the basic design is that EL1 is where privileged system code runs, and EL0 is where unprivileged user code runs. Thus EL0 is by necessity far more restricted in what it can do, and wouldn't be very useful for handling architectural exceptions, i.e. low-level things requiring detailed knowledge of the system. Only privileged software (typically the OS kernel) should have access to the full hardware and software state necessary to decide whether handling that basic hardware exception means e.g. going and quietly paging something in from swap, versus delivering a "software exception"-type signal to the offending task to tell it off for doing something bad.

Upvotes: 1

Related Questions