Reputation: 1734
I was trying to learn makefiles, and I am unable to get inference rules to work.
As per my knowledge , the inference rule below would make a *.o file from *.c file.
.c.o :
$(CC) $(CFLAGS) –c $@
Whenever I tried typing in "make temp.c" , it says no targets found AND when I tried to do "make temp" , it uses the default make command which is built inside make. How can I force makefiles to use my inference rules?
Upvotes: 1
Views: 1310
Reputation: 16540
make should have used your make file.
What is the file name of your make file?
make will only, automatically, find 'makefile' and 'Makefile'
Then you can write the command line as:
make myTarget
If you have used any other name, then you need to write that command line as:
make -f myMakefile myTarget
Upvotes: 1
Reputation: 206607
To be able make temp.o
given temp.c
, the rule needs to be:
.c.o:
$(CC) $(CFLAGS) -c -o $@ $<
or, if you use GNU Make,
%.o: %.c:
$(CC) $(CFLAGS) -c -o $@ $<
Upvotes: 2