CODEWITHSUNDEEP
verilog
Jpwang
Jpwang

Reputation: 143

How do I fix this error? Syntax error near "assign"

I'm trying to make a 2x1 mux in Verilog, with the variation that each input is actually technically 2 inputs, and same goes for the output. However, it still behaves like a 2x1 mux. My code looks like this:

module mux                                                      
(
  output [11:0] out_0,
  output [11:0] out_1,
  input sel,
  input [11:0] in_a_i,
  input [11:0] in_b_i,
  input [11:0] in_a_q,               
  input [11:0] in_b_q
)                    
  assign out_0 = (sel) ? in_a_i : in_b_i;             
  assign out_1 = (sel) ? in_a_q : in_b_q;                          
endmodule

When I try to build this in Xilinx, I'm given the error:

Syntax error near "assign"

I don't understand what's wrong with the assign line. Am I just missing something simple?

Upvotes: 0

Views: 987

Answers (1)

wilcroft
wilcroft

Reputation: 1635

Missing a semicolon (;) after the module declaration.

module mux
(
  output [11:0] out_0,
  output [11:0] out_1,
  input sel,
  input [11:0] in_a_i,
  input [11:0] in_b_i,
  input [11:0] in_a_q,               
  input [11:0] in_b_q
)  ;

Upvotes: 1

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