CODEWITHSUNDEEP
basherror-handlingmakefile
user3409642
user3409642

Reputation: 97

Makefile error message custom

I have some problem with a makefile. I just want to test if the compilation on src/launcher.c failed or not. But before that, i just can't convert this bash code:

out=$(gcc -c src/launcher.c -o /obj/launcher.o 2>&1)

To "Makefile code"

in fact, i want to make something like that : Handling gcc warnings and output in a Bash Script but in a makefile

Please, if you have some ideas.

CC      = clang
RM      = rm -f

NAME        = automakefile

CFLAGS      += -Wall -Wextra
CFLAGS      += -O2 -march=native -fomit-frame-pointer

LDFLAGS     +=

OBJS_DIR    = ./obj/
SRCS_DIR    = ./src/

INCLUDES    += -I ./src/include

OBJS_FILES  = launcher.o

OBJS        = $(foreach obj,$(OBJS_FILES),$(OBJS_DIR)$(obj))

all: script $(NAME)

script:
    @if [ ! -d "$(OBJS_DIR)" ]; then    \
        mkdir $(OBJS_DIR);      \
    fi

$(NAME): $(OBJS)
    $(CC) $(CFLAGS) $(OBJS) -o $(NAME) $(LDFLAGS)

$(OBJS_DIR)%.o: $(SRCS_DIR)%.c
    //This line isn't working!
    $(eval TMP=$$(gcc -c src/launcher.c -o obj/launcher.o 2>&1))
    echo $(TMP)

clean:
    $(RM) $(OBJS)

fclean: clean
    $(RM) $(NAME)

re: fclean all

.Phony: all script clean fclean re

Thanks Have a nice day

Upvotes: 0

Views: 2400

Answers (3)

Chnossos
Chnossos

Reputation: 10456

Make will automatically stop the compilation process whenever an error occur, but you can do with a message in case of warning or nothing bad happened:

$(OBJS_DIR)%.o: $(SRCS_DIR)%.c
    @$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $< &>output
    @if grep "warning" output >/dev/null ; then echo "$(<F) Warning" ; else echo "$(<F) OK" ; fi
    @$(RM) output

Here you go:

$(OBJS_DIR)%.o: $(SRCS_DIR)%.c
    @if $(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $< &>output; then \
        if grep "warning" output >/dev/null; then              \
            echo "$(<F) Warning(s)";                           \
        else                                                   \
            echo "$(<F) OK";                                   \
        fi;                                                    \
    else                                                       \
        echo "$(<F) Error(s)";                                 \
    fi
    @$(RM) output

Upvotes: 1

user3409642
user3409642

Reputation: 97

At the end, i used a little trick:

@$(CC) $(CFLAGS) -c $^ -o $@ $(INCLUDES) \
                && echo -e "\033[33;1m=== Compilation $@ \tSUCCEED===\033[0m"\
                || echo -e "\033[1;31m=== Compilation $@ \tFAILED===\033[0m"

Upvotes: 1

Etan Reisner
Etan Reisner

Reputation: 80921

make stops on target failure, you won't get any farther than the compilation that fails so you won't see anything beyond that.

If you are looking to "silence" the compilation a bit (so you don't see the compilation command itself) you could look into using something like my silent make rules makefile (based on the silencing support in recent autotools).

That won't hide output from the compilation commands themselves (warnings, etc.) but for successful/warning-free compilation there shouldn't be much output anyway and for failures/warnings you likely want to see it.

If you do want to do something like in your original link then you need to make sure that you hide the error code return from gcc in an if or similar (and capture it) and then exit with it again at the end of the recipe so that make still stops correctly.

Upvotes: 1

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