CODEWITHSUNDEEP
verilogassertverification
Plutonium smuggler
Plutonium smuggler

Reputation: 339

Assertions in verilog

I am new to verilog so please be easy.

Are assertions available in verilog ? Or are they a part of systemVerilog ?

Like most new comers, I have grabbed a book on verilog and it includes a chapter on verification ( which has assertions in it ; more than 2 dozens of them) . It also mentions OVL which I guess has some sort of header files ( or library containing these definitions) .

But google primarily displays results for assertions in systemVerilog not verilog. Add more to that, I am using Xilinx ISE 14.7 and Spartan 3A starter board as device . Xilinx Website mentions systemVerilog is supported only by Vivado design suite , but this suite does not support Spartan 3A board (I dont know systemVerilog either) .

So given all this, I am a little confused. How do I learn assert based verification in verilog . Is such thing even there in verilog ( I assume it's there in verilog because it's a verilog book )? . Is there some way I can do this is xilinx ise 14.7 ? I also have access to modelsim student edition for simulation, if that can help.

Upvotes: 0

Views: 2274

Answers (1)

dave_59
dave_59

Reputation: 42623

Assertion constructs were added to the SystemVerilog Language, not Verilog. However, an assertion is just statement of truth, and any self-checking testbench could be called a collection of assertions.

Assertion constructs in SystemVerilog provide a formalized standard for writing temporal expressions for testing their validity, plus a standardized metric for coverage reporting - i.e. not only tells if the assertion passed or failed, but how far it was exercised or not.

The OVL library is library of assertion expressions written in a variety of languages including Verilog and SystemVerilog. The SystemVerilog flavor is naturally more efficient, plus it gives you the additional coverage metrics.

Upvotes: 2

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