CODEWITHSUNDEEP
vhdl
KB Rajput
KB Rajput

Reputation: 3

VHDL - How to Define Port Map of a component with a package in its entity?

I am trying to use packages to shift block of data within different components via top level entity.

I have defined a package with array as

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package my_array_pkg is
 type my_array is array ( 0 to 9) of std_logic_vector(3 downto 0);
end my_array_pkg;

Then in top level entity I have declared my components as,

COMPONENT Array_Count is
Port ( C_1Hz    : in std_logic;
        reset : in std_logic;
        digit  : out my_array
        );
end COMPONENT;

Now can someone help me about how to declare this "digit : out my_array" in the port map. 

C2 : Array_Count
    PORT MAP ( CLK1HZ, RESET, ????);

The array package needed to be updated in other component.

Thanks.

Upvotes: 0

Views: 1112

Answers (1)

user1818839
user1818839

Reputation:

You need to "use" the package before the entity declaration : 

use work.my_array_pkg.all;

or 

library my_library; 
use my_library.my_array_pkg.all;

to make the package contents visible.

Then you need to declare a signal of that type before you instantiate the component, for example:

signal my_digit : my_array;

and now connect the port to that signal

C2 : Array_Count
    PORT MAP ( 
        C_1Hz => CLK1HZ, 
        reset => RESET, 
        digit => my_digit);

Upvotes: 2

Related Questions