CODEWITHSUNDEEP
makefile
Alexander Chen
Alexander Chen

Reputation: 507

Separated compilation with multiple sources by Makefile

I wrote a simple Makefile to compile several type of sources. And it works well. This Makefile will find all the protobuf sources and C++ sources. So making the program will act as follow.

  1. protoc will generate C++ sources files with *.proto
  2. g++ will compile object files with *.cpp and *.pb.cc (generated by step 1)
  3. g++ (actually is ld) will link all the object *.obj to a single executable

This Makefile sample is:

# Define the protoc generator
PROTOC = protoc
INCLUDE = -I$(SOMEPLACE) 
LIB = -lxml2  -lpthread -lz

# The final single outputted executable
OUTPUT  = svrkit_adapter_v2

# Define the cpp source code/object result
SOURCES = $(wildcard *.cpp)
OBJECTS=$(SOURCES:.cpp=.o)

# Define the proto's source/generated result/object result
PROTO_SOURCES = $(wildcard *.proto)
PROTO_CPPSRC = $(patsubst %.proto,%.pb.cc,$(PROTO_SOURCES))
PROTO_OBJECT = $(patsubst %.proto,%.pb.o,$(PROTO_SOURCES))

# First actual making target
all:$(OUTPUT) 

# Define the rule for generating proto's cpp sources
$(PROTO_CPPSRC) : $(PROTO_SOURCES)
  $(PROTOC) --cpp_out=. $(filter %.proto, $^) 

# Define the rule for compiling generated proto cpp sources
$(PROTO_OBJECT) : $(PROTO_CPPSRC)
  $(CXX) $(CPPFLAGS) $(INCLUDE) -c $(filter %.cc, $^) 

# Define the rule for compiling other cpp sources
$(OBJECTS): $(SOURCES) $(PROTO_OBJECT)
  $(CXX) $(CPPFLAGS) $(INCLUDE) -c $(filter %.cpp, $^) 

# Define the rule for linking the final executable
$(OUTPUT): $(OBJECTS) $(PROTO_OBJECT)
  $(CXX) $(CFLAGS) -o $@ $^ ${LIB}

clean:
  rm -f *.o *.~ *.bak *.pb.*
  rm -f $(OUTPUT)

However the command lines executed by make are as follow (for example):

protoc a.proto b.proto
g++ -c a.pb.cc b.pb.cc
g++ -c x.cpp y.cpp z.cpp
g++ -o output a.o b.o x.o y.o z.o

Sometime it works well. But if the sources are too many, it will cost a lot of time to recompile some unchanged sources. For example, I just modified a.proto and the Makefile will also recompile b.proto.

My question is: how can I make each source file be compiled/generated separately. The executed command lines should be:

protoc a.proto
protoc b.proto
g++ -c a.pb.cc -o a.o
g++ -c b.pb.cc -o b.o
g++ -c x.cpp -o x.o
g++ -c y.cpp -o y.o
g++ -c z.cpp -o z.o
g++ -o output a.o b.o x.o y.o z.o

Thanks in advanced.

Upvotes: 2

Views: 985

Answers (2)

DevSolar
DevSolar

Reputation: 70263

You make the mistake of having rules working on complete lists instead of individual files, taking away make's ability to work on individual files.

Your generation rules:

# Define the rule for generating proto's cpp sources
$(PROTO_CPPSRC) : $(PROTO_SOURCES)
  $(PROTOC) --cpp_out=. $(filter %.proto, $^) 

# Define the rule for compiling generated proto cpp sources
$(PROTO_OBJECT) : $(PROTO_CPPSRC)
  $(CXX) $(CPPFLAGS) $(INCLUDE) -c $(filter %.cc, $^)

Instead, make the rules work on individual files.

# Define the rule for generating proto's cpp sources
%.pb.cc: %.proto
    $(PROTOC) --cpp_out=. $<       

# Define the rule for compiling generated proto cpp sources
%.pb.o: %.pb.cc
    $(CXX) $(CPPFLAGS) $(INCLUDE) -c $< -o $@

The same goes for your C++ sources:

# Define the rule for compiling other cpp sources
$(OBJECTS): $(SOURCES) $(PROTO_OBJECT)
  $(CXX) $(CPPFLAGS) $(INCLUDE) -c $(filter %.cpp, $^)

(Why is $(PROTO_OBJECT) included in the dependencies? This looks very wrong to me.)

Again, switch this to work on individual files instead of whole lists:

# Define the rule for compiling other cpp sources
%.o: %.cpp
    $(CXX) $(CPPFLAGS) $(INCLUDE) -c $< -o $@

Only the final target needs the full list of objects:

# Define the rule for linking the final executable
$(OUTPUT): $(OBJECTS) $(PROTO_OBJECT)
  $(CXX) $(CFLAGS) -o $@ $^ ${LIB}

Drop PROTO_CPPSRC, it is not needed.

Now, make will look at that last rule, find the object dependencies, and will apply the single-file rule on each object that needs rebuilding.

Unrelated to your question, but while you're at it, add the following statement to your Makefile:

.PHONY: all clean

This will make "all" and "clean" to run always, even if a file with that name exists. This is not often a problem, but when it happens, it can be confusing as heck. ;-)

Upvotes: 5

PinkFloyd
PinkFloyd

Reputation: 2193

I know this is not the whole answer to your question but I think it could help you. Here is an example of the makefile I use :

EXEC=prog1
EXEC+=prog2

prog1_SRCS=prog1.cpp source1.cpp source2.cpp
prog2_SRCS=prog2.cpp source3.cpp

#------------------------------------------------------------------
#no need to change anything below that line (maybe add some OPTION)

CXX = g++ -std=c++11

ERRORS = -Wall -Wextra -pedantic
OPTION = 

BUILD=build

CXXFLAGS = $(ERRORS) $(OPTION)
LDFLAGS  = $(ERRORS) $(OPTION)

SRCS=$(wildcard *.cpp)

all: OPTION += -O3 -DNDEBUG
all:$(EXEC)

debug: OPTION += -ggdb 
debug:$(EXEC)

.SECONDEXPANSION:
$(EXEC): $$(patsubst %.cpp, $(BUILD)/%.o, $$($$@_SRCS)) 
    @echo Links $(notdir $^)
    $(CXX) -o $@ $^ $(LDFLAGS) 

$(BUILD)/%.o:%.cpp
    @echo Creates $(notdir $@)
    $(CXX) -MD -c $(CXXFLAGS) $< -o $@

-include $(addprefix $(BUILD)/,$(SRCS:.cpp=.d))

clean:
    rm -f $(BUILD)/* $(EXEC)

you'll need a directory called build to save .o and .d file. they will allow you to recompile only the files that have been modified

Upvotes: 0

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