CODEWITHSUNDEEP
compilationvhdlstandards
DylanM
DylanM

Reputation: 343

VHDL - Conditional compilation

My VHDL testbench uses some features that are specific to VHDL'2008 but, depending on what exactly I'm testing or which software I'm using for the simulation, it cannot always be compiled in VHDL'2008.

To cope with that, I created 2 versions of this testbench :

However, maintaining two nearly identical versions of this testbench is really an annoying thing to do, so I would like to merge them in some way.

I first thought I could use a generic and an "IF .. GENERATE" statement but this obviously doesn't allow me to '93-compile a file with '2008 features.

Is there a way to merge these 2 files and still compile the result with VHDL'93 ?

Upvotes: 2

Views: 2530

Answers (1)

suoto
suoto

Reputation: 479

Option 1 -- Pragmas

If the code that uses VHDL 2008 doesn't replaces other pieces of the code (i.e., the code using VHDL 2008 does extra stuff), you can use pragmas such as

vhdl_93_component_u : foo_93 port map ( clk => clk, out => out);
-- rtl_synthesis off
vhdl_2008_component_u : foo_2008 port map ( clk => clk, out => out);
-- rtl_synthesis on

Also, check if your tool accepts enabling and disabling interpretation of pragmas and which pragmas it accepts. -- rtl_synthesis on/off is an example here.

Option 2 -- Different files

If you can split your code in 3 (testbench top, VHDL '93 code, VHDL 2008 code), you can compile only the file you need (assuming same package/architecture/entity names).

If you can't refactor your code to use something like this, I suggest you review the way you are implementing your testbench.

Upvotes: 1

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