CODEWITHSUNDEEP
microcontrollercpu-architectureriscv
Aneesh Raveendran
Aneesh Raveendran

Reputation: 391

System instruction working

I am trying to implement a simple RISC-V 32-bit core with user level instructions.

while trying to implement ISA, I found an instruction (system) in the listing. can anybody explain the working of system instruction(what changes will come in pipeline).

Upvotes: 0

Views: 251

Answers (1)

CliffordVienna
CliffordVienna

Reputation: 8235

SYSTEM is a so-called major opcode. Some major opcodes are instructions by themself (LUI, AUIPC, JAL, JALR), but most major opcodes are spaces for instructions. So is SYSTEM. In RV32I the instructions SCALL, SBREAK, RDCYCLE, RDCYCLEH, RDTIME, RDTIMEH, RDINSTRET, RDINSTRETH are all encoded using the major opcode SYSTEM (i.e. the bits 6:0 of the instruction word are 1110011 for this instructions).

See the tables and explanations on pages 49 and 50 in The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0 for details.

Upvotes: 5

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