freddy418
Reputation: 1
SystemVerilog: How to model clock period of 0.5ns given 1ns `timescale precision
Given my understanding of how timescale precision is used to schedule events in System Verilog. Is it possible for this to be done without resorting to multiplying all delays?
Upvotes: 0
Views: 625
Answers (1)
dave_59
Reputation: 42738
You need at least 100ps time precision to represent 0.5ns. Your clock generator can be put in a module with that precision and all other modules will adjust their precision to the smallest precision of all modules.
Upvotes: 0
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