CODEWITHSUNDEEP
assemblyx86processor
golem
golem

Reputation: 1930

What are examples of practical usage of x86 processor interrupt flag?

Wikipedia says that interrupt flag determines whether or not the CPU will handle maskable hardware interrupts. If the flag is set to 1, maskable hardware interrupts will be handled, If cleared - ignored.

I'm having difficulty understanding what is maskable or non-maskable interrupt.

  1. What are practical usages of the IF flag?
  2. What is maskable/non-maskable interrupt and what's the difference?

P.S. I'm just starting to delve into Assembly language and inner workings of the processor, so plain English as for 5 years old please. If it is possible of course =).

Upvotes: 1

Views: 903

Answers (2)

Peter Cordes
Peter Cordes

Reputation: 365747

If you're learning asm to speed up inner loops and stuff, you don't need to worry about it. You can and should leave interrupt-management to the OS. (cli / sti are of course privileged instructions that only work for the kernel anyway.)

Linux Device Drivers (2nd Edition), Chapter 9 is about interrupt handling, and mentions using cli/sti.

In the pre-SMP days, disabling interrupts worked as a simple brute-force alternative to locking. With multi-core CPUs, another core could touch your data structure even while interrupts are disabled on the core your code is running on, so it's a lot less useful. It's very rarely done anymore.

There are some times when disabling interrupts is necessary. For example, while you do something which temporarily has the stack pointer not pointing to valid memory. (nvm, mov ss, reg implicitly disables interrupts until after the following instruction. So you can change the stack segment and then the stack pointer without a cli/sti. Which is irrelevant in 64bit code, where the segment registers are essentially unused.)

Another possible example is while modifying other key data structures that the CPU uses to decide what to do when an interrupt happens. (global descriptor table and/or interrupt descriptor table). Although IDK about those, if they're shared with other CPUs then you'd need to keep them always valid. I think I read an example not too long ago about a case where you needed to disable interrupts during some pair of connected changes to descriptor tables or something, but I can't remember what.

I'm not really an i386 expert on kernel-space stuff, so I don't grok everything in this explanation of a case where you need to disable interrupts when using "task gates", whatever those are.

This doc looks like it's part of a low-level tutorial series: http://www.osdever.net/bkerndev/Docs/gdt.htm. You might find it interesting if you want to dig into all the crazy stuff that happens under the hood on x86.

Upvotes: 2

500 - Internal Server Error
500 - Internal Server Error

Reputation: 28839

A typical scenario e.g. in DOS programming is where you disable interrupts before you modify the interrupt handler table and reenable interrupts when you are done.

If interrupts were allowed to occur when you were modifying the table, you wouldn't know if the old or the new handler address (or half of each) was going to be used.

You can also have situations where you want to disable interrupts within an interrupt handler itself to prevent it from being called again while you are servicing the pending interrupt.

Non-maskable interrupts are generally ones that occur regardless of the current status of the interrupt flag - I don't recall having ever had to deal with those.

Upvotes: 4

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