VHDL : No comparison operator available at all (used in binary to thermometer design)

I've wasted hours on looking for a single working definition on ANY comparison operator: This is always the compiler answer (minus the varying operator) : "found '0' definitions of operator ">=", cannot determine exact overloaded matching definition for ">=""

Here's the tiny code:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--USE IEEE.NUMERIC_STD.ALL;

ENTITY dec IS
  PORT ( bin : IN std_logic_vector (9 DOWNTO 0);
       unary :OUT std_logic_vector (1022 DOWNTO 0));
END dec;

ARCHITECTURE rtl OF dec IS

BEGIN
  G: FOR i IN 0 TO 1022 GENERATE
    unary(i) <= ( bin >= i );
  END GENERATE G;
END rtl;

Changing everything for the libraries to the "bin" signal type to the ONLY relevant statement "unary(i) <= ( bin >= i )" (using casts, changing the operation (even though it's useless other than maybe for debugging), swapping operands, and so on). Even using any combination of those variations (all those I've tried so far - and there's a lot of them), none are an existing definition of any comparison operator.

Hopefully that question is clear enough, thanks.

Upvotes: 1

Views: 591

Answers (1)

Paebbels
Paebbels

Reputation: 16249

First of all:
Don't use STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED. These packages are obsolete.

Use NUMERIC_STD that's enough. It comes with an UNSIGNED and SIGNED type as well as operators for these types.

Secondly - like in every other language - a comparision operator returns a boolean value, no STD_LOGIC or BIT.

Last but not least: Arithmetic operators are only defined on 'arithmetic types' like UNSIGNED or SIGNED. So a cast is needed to compare a STD_LOGIC_VECTOR with an INTEGER.

Rewritten code:

gen : for i in unary'range generate
  unary(i) <= '1' when (unsigned(bin) >= i)) else '0';
end generate;

Upvotes: 2

Related Questions