CODEWITHSUNDEEP
makefilenaming-conventionsgnu-make
Waqas Ilyas
Waqas Ilyas

Reputation: 3241

Is there a naming convention for makefile targets and variables

I couldn't find anything in the GNU Makefile Conventions.

Upvotes: 32

Views: 16564

Answers (3)

qwr
qwr

Reputation: 10958

Makefile's implicit rules use a set of common variable names which are used by convention for explicit rules, such as:

  • CC: C compiler
  • CFLAGS: C compiler flags
  • CXX: C++ compiler (CPP is for C preprocessor)
  • CXXFLAGS: C++ compiler flags
  • LDFLAGS: Extra flags for linker, such as -L
  • LDLIBS: Library flags, such as -lm

Use make -p in a directory without a Makefile to see your system's predefined variables.

Upvotes: 3

Florent Roques
Florent Roques

Reputation: 2662

This is the implicit naming convention followed by GNU Makefile documentation:

Targets

Target names should use lower case letters. Words are separated with a hyphen - or not separated. E.g.:

test-debug:
    $(build_dir)/debug/bin

or

testdebug:
    $(build_dir)/debug/bin

Variables

Variables that are not special to make, and that are not inherited from the environment, should be in lowercase. Words should be separated with underscore symbol _. E.g.:

src_dir = $(CURDIR)/src
build_dir = $(CURDIR)/build

References:

Makefile style guide (based on GNU Makefile documentation)

GNU Makefile Standard Targets

  • targets: you can find targets like install, install-strip, installcheck

  • variables: you can read "This includes the directories specified as the values of the variables prefix and exec_prefix" within the install target documentation

Upvotes: 32

user4713908
user4713908

Reputation:

The most used (I think) are all, clean, compile, run, install, test, and all common task that you may need to build whatever you're buinding.

You could study makefiles inside big projects such as Linux, Vim, etc, but if you want to get standards into your project you will want to use Autotools as well.

For small projects, I usually use meaningful names based on the context, so I can do something like this:

$make compile   (to compile)
$make lib       (to create the libraries)
$make link      (to link the objects into the executable)
$make run       (to run the program)
$make all       (to make all of them at once)

and, to make this happen as expected, I have to insert dependencies like:

all: run

run: link
    # Instructions for run

link: lib
    # Instructions for link

lib: compile
    # Instructions for make the lib

compile:
    #Instructions for compilation

Upvotes: 6

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