Chris88
Reputation: 27
VHDL unnecessary value after (to_unsigned) conversion
I use a for loop:
for l in 0 to 2 loop
and inside I want to have at some point 2 when l=0, 1 when l=1 and 0 when l=2. How can I do that? I used:
to_integer(unsigned(not(std_logic_vector(to_unsigned(l,2)))))
[which seems too complicated] but there is an error at simulations. I think because the final integer can also take the value 3. The error is:
Value 3 is out of range 0 to 2.
Upvotes: 0
Views: 172
Answers (1)
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