CODEWITHSUNDEEP
verilogcalculatorquartus
Charles B
Charles B

Reputation: 15

Can't identify unsafe latch behaviour or completeness of case statement in Verilog code

Hey I'm trying to create a small module that reads which button is pressed on a DE2 4x4 matrix board and then display which column and which row is being pressed on the LED's but I'm having a few problems.

Right now the Columns work but not the rows. I think it has something to do with the fact that the LEDS I use to display the row status have "unsafe latch behaviour" but I'm not too sure.

I have also noticed that for my case statement only ever resolves to the default statement and I don't know why and it says it can't check for completeness.

Would anybody be able to help me? If so thank you very much.

module MatrixInput(MInput, MOutput, LEDR);
input [16:10] MInput; //cols
output reg [24:18] MOutput; //rows
output reg [7:0] LEDR;
reg [31:0] counter; //just setting to max size for now
reg [31:0] i;
reg LEDFlag;

initial begin
    counter = 0;
    i = 7;
    LEDFlag = 0;
end



always@(*) begin

    case(counter)
        0: MOutput = 7'b0x1x1x1;
        1:  MOutput = 7'b1x0x1x1;
        2:  MOutput = 7'b1x1x0x1;
        3:  MOutput = 7'b1x1x1x0;
        default: MOutput = 7'b1x0x0x0;
    endcase

    LEDR[7] = MInput[10];
    LEDR[6] = MInput[12];
    LEDR[5] = MInput[14];
    LEDR[4] = MInput[16];


    repeat(4) begin //step through each col 
        if (LEDR[i] == 1) //set the LED flag on if any of the col LEDS on
            LEDFlag = 1;
        if (i != 3) //count down from 7 to 3
            i = i - 1;
        else
            i = 7;
    end

    LEDR[counter] = LEDFlag;
    LEDFlag = 0;

    if (counter != 4)
        counter = counter + 1;
    else
        counter = 0;

end
endmodule

Upvotes: 1

Views: 269

Answers (1)

Jason Yu
Jason Yu

Reputation: 61

There are a number of issues here, I'll give you some hints to get started. Number one is you need some kind of clock to make the counter actually count in a way that you can observe. Otherwise it just zips around like an infinite loop in software (actually, the synthesis tool is probably smart enough to see this and not synthesize any logic at all). Second, initial works only in simulation, but it is not a synthesizable construct. When you power up the logic, counter is going to be at some random value which will likely not match any of the 0-3 cases you have defined, which is why it always goes to the default case. You need a reset and to specify a reset value.

Upvotes: 1

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