CODEWITHSUNDEEP
verilogseven-segment-display
user4134614
user4134614

Reputation:

4bit number to seven segment

I have a 4 bit output number as output. How can it be seen on seven segment display as hexadecimal number? I'm new and mentioning verilog. So, I have a four bit binary number and want to display it as hexadecimal. Ex. 1010(10) as A

case example:

wire [3:0] num;
case (num)
  4'b0000 : 1111110;
  4'b0001 : 0110000;
  4'b0010 : 1101101;
  4'b0011 : 1111001;
  so on
  .
  .
  4'b1111 : 1000111;
endcase

enter image description here

4 bit binary to seven segment

#TABLE: x1,x2,x3,x4 => a,b,c,d,e,f,g

0000 => 1111110

0001 => 0110000

0010 => 1101101

0011 => 1111001

0100 => 0110011

0101 => 1011011

0110 => 1011111

0111 => 1110000

1000 => 1111111

1001 => 1111011

1010 => 1110111

1011 => 0011111

1100 => 1001110

1101 => 0111101

1110 => 1001111

1111 => 1000111

Upvotes: 0

Views: 2689

Answers (1)

Greg
Greg

Reputation: 19094

In Verilog, if you do not define the base type of a number, it will assume decimal. Ex: 10 is decimal ten not binary two. A case statement should be defined in a always block. 

reg [6:0] led;
wire [3:0] num;
always @* begin
  case (num)
    4'b0000 : led = 7'b1111110;
    /* you fill in the rest */
    4'b1111 : led = 7'b1000111;
  endcase
end

Upvotes: 1

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