CODEWITHSUNDEEP
arraystruncatesystem-verilog
João
João

Reputation: 13

Assign and Truncate Packed Arrays

Recently I've been coding an FFT module, and as you may think it requires a lot of wires. In order to simplify the code I'm trying to use packed arrays. But I got a problem in truncating and assigning. Suppose I have a 48-bit vector A, divided into 6 8-bit sub-fields:

logic [5:0][7:0] A;

Now, consider I have another vector B, which is 24-bit long, divided into 6 4-bit sub-fields:

logic [5:0][3:0] B;

Now the question is, how to assign the 4 MSB of each sub-field in A to the correspondent sub-field in B (preferably without using for loops)?

Upvotes: 1

Views: 633

Answers (1)

dave_59
dave_59

Reputation: 42623

Unfortunately, there is no special syntax in SystemVerilog to do this kind of lossy assignment in a single assignment.

Upvotes: 1

Related Questions