CODEWITHSUNDEEP
verilog
Noober
Noober

Reputation: 1626

Syntax Error in verilog

I am trying to use genvar in verilog. Here is part of my code-

reg [31:0] q[0:3];
initial
begin
   genvar j;
   generate
   for(j=0;j<4;j=j+1) begin : loop1
      q[j]=32'H00000000;
   end
   endgenerate
end

This gives a syntax error-

Error:near "genvar":syntax error,unexpected "genvar"

How can I implement this?I want to initialize all q array with all zeros in all 32 bits. I want to do this through a loop as size of array can be very large.

Upvotes: 0

Views: 1464

Answers (1)

sharvil111
sharvil111

Reputation: 4381

First of all, generate block is usually used along with for loops to mimic multiple instants.

You have used generate in the initial procedural block, which is obviously illegal. And hence the syntax error occurs. So, remove genvar and generate block.

To initialize the variable, there can be many methods. Some of them are as follows.

reg [31:0] q[0:3] = '{0,1,2,3}; // assigning default values

reg [31:0] q[0:3];
initial
begin                        // weird method
   for(j=0;j<4;j=j+1) begin : loop1
      q[j]=32'h00000000;
   end
end

reg [31:0] q[0:3];
initial
begin
  q='{default:'0}; // initialize all elements to zero
end

reg [31:0] q[0:3];
initial
begin
  foreach(q[i]) // can be preferable
    q[i] = 0;
end

Refer to SystemVerilog LRM 1800-2012 for more info on generate block.

Upvotes: 4

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