CODEWITHSUNDEEP
arrayssystem-verilog
user4061565
user4061565

Reputation: 545

Systemverilog breakout array of interfaces

I have a lower level module that implements an array of interfaces. At a higher level I would like to break out that interface array and assign it to individual ports (the code is just an example . . . no special functionality intended).

// -------- INTERFACE --------
interface my_if;
    logic   d;
endinterface

// -------- INTERMEDIATE MODULE --------
module intermediate(
    my_if   i1,
    my_if   i2
    );

    sub mySub(
        .a   ('{i1,i2}),
        .w1  (1'b1)
    );
endmodule

// -------- SUB MODULE --------
module sub(
    my_if         a[2],
    input wire    w1
    );

    assign a[0].d = w1;
    assign a[1].d = ~w1;
endmodule

The above code gives me an error:

The interface port 'a' of module 'sub' whose type is interface 'my_if' is illegally connected.

Two questions:

  1. how can I implement the above?
  2. how do I assign an interface to another of the same type? ie in the code above I tried assigning and aliasing the array interface to an intermediate one (alias i1 = ii[0]) . . . but I can't figure out how to do that.

Upvotes: 1

Views: 1549

Answers (1)

dave_59
dave_59

Reputation: 42616

This is not allowed in SystemVerilog. There is a real problem with interfaces in that you cannot compose one interface from a collection of other interfaces.

The only workaround is using assign statements that would connect the signals in an individual interface ports to the signals in the array of interface signals.

You would be better of not using interface and perhaps use a struct instead.

Upvotes: 1

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