CODEWITHSUNDEEP
vhdl
Prof. Hell
Prof. Hell

Reputation: 809

Are guarded signals unsupported in block statement?

I have 4 errors in the lines of this code:

architecture guard of FlipFlop is
begin
    bb: block(clk='1' and not clk'stable) is   -- errorHDLParsers:1074 Guarded signal unsupported in block statement.
    begin
        Q <= guarded D after tpl;     -- errorHDLParsers:1024 Guarded unsupported in signal assignment.
        Qb <= guarded not D after tph;  -- errorHDLParsers:1024 Guarded unsupported in signal assignment.
    end block bb;
end guard;

architecture guard2 of FlipFlop is
begin
    bb: block(clk='1' and not clk'stable) is  -- errorHDLParsers:1074 Guarded signal unsupported in block statement.
    begin
        Q <= D after tpl;
        Qb <= not D after tph;
    end block bb;
end guard2;

Why can't I define a block with guarded signals?

Upvotes: 1

Views: 1045

Answers (1)

Martin Zabel
Martin Zabel

Reputation: 3659

It seems that your synthesis tool does not support this VHDL statement. I have checked the first architecture guard with integrated synthesizer of the Quartus-II 13.1 Web Edition for Windows and it works here. It is not unusual that the synthesis tools only provide a subset of the VHDL language.

I prefer to use a clocked process instead:

process(clk)
begin
  if rising_edge(clk) then
    Q <= D;
    Qb <= not D;
  end if;
end process;

The signals Q and Qb get there new values after the process has finished. Thus, the assignments use the value of D just before the rising clock edge.

Please note, that I have omitted the after xy delay. The actual timing is defined by the flip-flop built into the FPGA. Thus the specified delay is just ignored by synthesis tools. It is used only for RTL simulation.

EDIT: The second architecture guard2 does not describe a flip-flop because the guard condition of the block does only control guarded signal assignments. Thus the code is equivalent to:

Q <= D;      -- after tpl
Qb <= not D; -- after tph

Upvotes: 3

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