issues with Makefile in C

Question

    #-----------------------------------------------------------------------    ------
# Choose a compiler & its options
#--------------------------------------------------------------------------

CC   = gcc
OPTS = -W -O3

#--------------------------------------------------------------------------
# Add the debug flag to compile for use by a debugger
#--------------------------------------------------------------------------
#DEBUG=-g

#--------------------------------------------------------------------------
# Add the names of the directories
#--------------------------------------------------------------------------
SRCDIR= src
OBJDIR= obj
INCDIR= include
BINDIR= bin

#--------------------------------------------------------------------
# Add the rest of the source files. Don't forget to add the '\' character
# to continue the line. You don't need it after the last source file
#--------------------------------------------------------------------
SRCS=$(SRCDIR)/Lab12.c \ Function1.c \ Function2.c \ Function3.c \                                   Function4.c \          Function5.c 

#--------------------------------------------------------------------
# You don't need to edit the next few lines. They define other flags
# used in the compilation of the source code
#--------------------------------------------------------------------
INCLUDE = $(addprefix -I,$(INCDIR))
OBJS=${SRCS:$(SRCDIR)/%.c=$(OBJDIR)/%.o}
CFLAGS   = $(OPTS) $(INCLUDE) $(DEBUG)

#--------------------------------------------------------------------
# Add the name of the executable after the $(BINDIR)/
#--------------------------------------------------------------------
TARGET = $(BINDIR)/ Lab12

all: $(TARGET)

$(TARGET): $(OBJS) 
    ${CC} ${CFLAGS} -o $@ $(OBJS)

$(OBJS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
    $(CC) $(CFLAGS) -c $< -o $@

clean:
    rm -f $(OBJS)

 cleanall:
    rm -f $(OBJS)
    rm -f Lab12

 #--------------------------------------------------------------------
 # Add a target named cleanall that will remove the object files as well
 # as the executable
 #--------------------------------------------------------------------

I have all my "header" files in the include folder. I have all my source code in the src folder (Lab12.c , Function1.c, Function2.c ...). I keep getting this error when i use the make command.

Makefile:45: target Function1.c' doesn't match the target pattern Makefile:45: target Function2.c' doesn't match the target pattern Makefile:45: target Function3.c' doesn't match the target pattern Makefile:45: target Function4.c' doesn't match the target pattern Makefile:45: target ` Function5.c' doesn't match the target pattern gcc -W -O3 -Iinclude -c -o Function1.c gcc: no input files make: *** [ Function1.c] Error 1

I cant quite figure out why it is behaving this way. All these files are in the src code folder so why isnt the system recognizing them?

Answer 1

SRCS=$(SRCDIR)/Lab12.c \ Function1.c \ Function2.c \ Function3.c \

seems wrong; you should try

SRCS=$(SRCDIR)/Lab12.c Function1.c Function2.c Function3.c

instead

UPDATE

If Function1.c and so on are in ´$(SRCDIR)`, you must prepend the directory to these files, too. (comment from M Oehm)