CODEWITHSUNDEEP
vhdlfpgahardware
Sebi2020
Sebi2020

Reputation: 2150

How to map a single bit of a signal to multiple bits of a Vector?

I've tried to map a bit of a signal (here addS of type signed(32 downto 0)) in a structural description like this:

add2 : entity work.adderSigned(behavioral) 
  generic map(N => 64)
    port map(a(63 downto 32) => mulssS, --concat 
        a(31 downto 0) => signed(muluuS), --concat
     -- b(63 downto 48) => addS(32 downto 32),
        b(63 downto 48) => (others => addS(32)), --the critical line
        b(47 downto 16) => addS(31 downto 0),
        b(15 downto 0) => (others => '0'),
        std_logic_vector(y) => y);

but the compiler complains that this isn't a static mapping. How can I perform this mapping?

Upvotes: 0

Views: 2518

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

In VHDL-2008 the line b(63 downto 48) => (others => addS(32)), is valid, so enable VHDL-2008 if the tool allows.

For VHDL-2002, if an expression is used as actual (right side in port map), then it must be a globally static expression (VHDL-2002 1.1.1.2 Ports), but (others => addS(32)) ain't, since addS(32) is not static. A work around can be:

signal b_63_dt_48 : std_logic_vector(63 downto 48);
...
b(63 downto 48) => b_63_dt_48,
...
b_63_dt_48 <= (others => addS(32));

Btw. looks like there may be some odd about the line std_logic_vector(y) => y.

Upvotes: 1

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