CODEWITHSUNDEEP
makefilegnu-make
Philip
Philip

Reputation: 121

Wildcard symbol in Makefile executing some targets but not others

From what I've been able to find, the wildcard symbol in a Makefile target : prerequisite line is a pattern rule that states "for every target X.o, if there exists a file named X.c (for example), do the following commands"

What I can't seem to figure out is why, in the Makefile below only one of the wildcard arguments is executed.

all : foo.o

%.o : %.c
    echo first %.o : %.c

%.o : %.c
    echo second %.o : %.c

foo.o: foo.c foo.h bar.h baz.h

When I run all, I get this output:

echo second %.o : %.c
second %.o : %.c

According to what I know, both wildcard statements should be displayed, as they both match the pattern. Can anyone explain why they aren't?

Upvotes: 1

Views: 516

Answers (1)

Tsyvarev
Tsyvarev

Reputation: 65898

The second %.o: %.c rule overrides the first one. That is why output for the first rule is not output.

From the gnu-make manual:

You can override a built-in implicit rule (or one you have defined yourself) by defining a new pattern rule with the same target and prerequisites, but a different recipe.

Upvotes: 1

Related Questions