CODEWITHSUNDEEP
bashvariablesmakefile
Wim
Wim

Reputation: 11242

Defining variables for use in both Makefiles and Shell scripts

I'd like to distribute a set of build variables (which someone should append to their LDFLAGS), in a form that can both be included in a Makefile and in a shell script.

What I have now is a file buildflags.conf:

LDFLAGS_EXTRA="-static -foo -bar"

I want my users to be able to, when they're using makefiles:

include buildflags.conf
LDFLAGS+=$LDFLAGS_EXTRA

Or, when they're using a shell script, do something like:

. buildflags.conf
gcc myapp.o -o myapp $LDFLAGS_EXTRA

This doesn't work however, since bash needs quotes around my LDFLAGS_EXTRA definition, while make does not want them.

Anyone with a solution for this? I don't want to maintain multiple separate buildflags files, although a set of scripts that start from a single definition file and make it suitable for inclusion in different contexts would be fine.

Upvotes: 2

Views: 1116

Answers (2)

Michel Müller
Michel Müller

Reputation: 5695

Ivo's solution in his comment has brought me to another one that works as well and is more canonical for Makefiles:

1) Define LDFLAGS_EXTRA as in the question

2) Post process the list for use in Makefiles

LDFLAGS_EXTRA_POST=$(subst ",,${LDFLAGS_EXTRA})

3) Make sure to only reference LDFLAGS_EXTRA_POST in Makefiles

Upvotes: 1

Ivo
Ivo

Reputation: 3569

I'd say the easiest solution is to just include the shell script containing the variable definitions in your make recipes (this works fine if your recipes are simple):

target: sources
    . buildflags.conf ; \
    gcc -o $@ $^ $$LDFLAGS_EXTRA

Note the extra $ in the variable usage and the fact that the two lines are in fact one statement, the ;\ is important.

Upvotes: 2

Related Questions