CODEWITHSUNDEEP
verilogsystem-verilogintel-fpga
MTMD
MTMD

Reputation: 1232

Adding header files in Verilog

I wanted to add a header file to my Verilog project. This should be a very easy thing to do. However, it turns out is is not trivial. This my header file. Let's say the file name is parameters.vh

`ifndef _parameters_vh_
`define _parameters_vh_
parameter Tm = 2;
parameter Tn = 2;
`endif

Then I include it to the top module

`include "parameters.vh"

But it cannot get synthesized. This is the error message:

Verilog HDL error at parameters.vh(3): declaring global objects is a SystemVerilog feature. I am wondering if anyone can help me here.

Upvotes: 1

Views: 21570

Answers (2)

Sam
Sam

Reputation: 11

it's not a systemverilog issue, just think of what the pre processor is doing when it finds your include line. you can't have parameters outside modules, doesn't make sense.

Upvotes: 1

Martin Zabel
Martin Zabel

Reputation: 3659

In Quartus-II, you can enable SystemVerilog features via menu Assignments -> Settings -> Verilog HDL Input.

Otherwise you have to move the inclusion of the parameters file within a module definition like here:

module top (x,y);
`include "parameters.vh"
   input x;
   output y;
   assign y = x;
endmodule // top

Upvotes: 3

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