CODEWITHSUNDEEP
verilog
ziba
ziba

Reputation: 53

I have magnitude comparator 4-bit Verilog code and I have wrong output

I have Verilog code: magnitude comparator 4-bit. I don't know what is wrong. I have output without (a great than b) and (a less than b). Where is my mistake?

`timescale 1ns/1ns
module magnitudecomparator(agtb,altb,aeqb,a,b);
  input [3:0]a,b;
 output agtb,altb,aeqb;
 wire [3:0]x;

 assign x=!(a^b);
 assign agtb=(a[3]&(!b[3]))|(x[3]&a[2]&(!b[2]))|(x[3]&x[2]&a[1]&(!b[1]))|(x[3]&x[2]&x[1]&a[0]&(!b[0]));
assign altb=((!a[3])&b[3])|(x[3]&(!a[2])&b[2])|(x[3]&x[2]&(!a[1])&b[1])|(x[3]&x[2]&x[1]&(!a[0])&b[0]);
assign aeqb=x[3]&x[2]&x[1]&x[0];
endmodule



`timescale 1ns/1ns
module testmagnitudecomparator;
 reg a,b;
 wire agtb,aeqb,altb;
 magnitudecomparator m0(agtb,altb,aeqb,a,b);
 initial
  begin
   #10 a=4'b0110;b=4'b1110;
   #20 a=4'b1101;b=4'b0111;
   #30 a=4'b1011;b=4'b1011;

 end
initial
$monitor($time, "THE VALUE OF INPUT  IS a=%b ,b=%b AND OUTPUT IS agtb=%b ,aeqb=%b ,altb=%b",a,b,agtb,aeqb,altb);
endmodule

Upvotes: 2

Views: 739

Answers (2)

badari259
badari259

Reputation: 27

Or you can also use a behavioral code by using if else statements.. 

always@(*)
  begin
     if(a>b)
       agtb=1'b1;
     else if(a<b)
       altb=1'b1;
     else
       aeqb=q'b1;
  end

Upvotes: 0

toolic
toolic

Reputation: 62164

In your testbench, you connected 1-bit signals to 4-bit ports. In the testmagnitudecomparator module, change:

 reg a,b;

to:

 reg [3:0]a,b;

Also, you could simplify your code:

assign agtb = (a >  b);
assign altb = (a <  b);
assign aeqb = (a == b);

Upvotes: 3

Related Questions