CODEWITHSUNDEEP
makefilegnu-make
Pushpendre
Pushpendre

Reputation: 835

How to make "%" wildcard match targets containing the equal sign?

The makefile wildcard system doesn't seem to match targets if they contain the equal sign. Is there a way to work around this deficiency? Some flag or setting or rule to escape the equal sign? I know I can just not use the equal sign but I'd prefer to fix this idiosyncrasy of make if possible.

Here's an example of what I mean

$ cat Makefile
all:
    echo Dummy target
b_%:
    echo $@

$ make b_c=1
  echo Dummy Target
$ make b_c1
  echo b_c1

The first make command does not match b_% even though it should. I also wasn't able to find documentation for exactly what is supposed to be matched by the % wildcard. Any pointers? My make version is

$ make --version                                               
GNU Make 3.81         
Copyright (C) 2006  Free Software Foundation, Inc.                                                                                                             
This program built for i386-apple-darwin10.0

Upvotes: 0

Views: 361

Answers (1)

tripleee
tripleee

Reputation: 189457

The problem here is not with the % syntax, but with the fact that any command-line argument with an equals sign in it is interpreted as a variable assignment.

You should find that if you add the dependency all: b_c=1, then make all will generate the file just fine.

There are restrictions on what file names you can use with make -- they can't contain spaces or newlines, and e.g. backslashes are problematic, too (though not completely impossible to accommodate for simple use cases).

If you absolutely have to have a file named like this, my suggested workaround would be to use a different name internally, and then symlink it to the external name as the last step of the make recipe.

Upvotes: 1

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