CODEWITHSUNDEEP
assemblymachine-codemnemonics
Shivam Aggarwal
Shivam Aggarwal

Reputation: 774

What is the difference between Mnemonics and Opcode

In assembly language under the instruction set of a 8085 microprocessor, suppose we have the following operation ADD B.
I know this means "Add the data of register of B to the Accumulator register and save the contents back to the Accumulator".

Upvotes: 0

Views: 4260

Answers (3)

Peter Cordes
Peter Cordes

Reputation: 364573

Some architectures have many different forms of the same mnemonic. Things should be much easier to understand when looking at an example from such an architecture.

e.g. x86 has 5 forms of 32bit add. (There are just as many forms for 8bit add, except of course that there isn't a 32bit immediate version. 16 and 64bit adds are encoded with prefix bytes in front of the 32bit encodings.)

Table format: OPCODE and operand encoding / MNEMONIC / OPERANDS (dest, src)

05 id ADD EAX, imm32    # special-case save-one-bye for adding to the accumulator

81 /0 id ADD r/m32, imm32
83 /0 ib ADD r/m32, imm8
03 /r ADD r32, r/m32    # src can be memory

01 /r ADD r/m32, r32    # dest can be memory

So for add eax, edx, there are two possible encodings: 01 D0 (picked by GNU as) or 03 whatever (looking up the encoding of the mod/rm byte for the operands in the other order is left as an exercise for the reader.)

The /0 means the unused src-reg bits in the mod/rm byte are borrowed as part of the opcode. 83 /4 ib is AND r/m32, imm8. When people say x86 machine code is nasty to decode, this is the kind of thing they're talking about (besides the variable-length nature, and the fact that optional prefix bytes mean the opcode isn't even the first byte... You have to mostly decode an instruction before you can even know how long it is to start decoding the next one. There's a reason parallel 4-wide decoding of x86 instructions is power-hungry.)

A more extreme case is that x86 uses mov for several different kinds of instructions, determined by the operands:

  • regular mov r32, r/m32 (or the reverse)
  • mov-immediate to register or memory
  • mov to/from segment registers (all three of these forms documented on the same page in the manual)
  • mov to/from control registers (even has a different entry in the manual)
  • mov to/from debug registers (another separate entry in the manual).

I can't think of a case where two different mnemonics produce the same opcode. But a single mnemonic can produce different opcodes with different operands.

The operand can even be encoded into the opcode byte for very commonly used instructions, to save space (this is SergeyA's answer). You could think of x86's B8 opcode as mov-imm32-to-eax. (the B8 to BF opcodes are all mov-immediate to register, each with a different destination reg.) 32bit x86 has single-byte opcodes for inc/dec of registers. x86-64 repurposed that contiguous range of 16 opcodes for use as REX prefix bytes (leaving the two-byte inc r/m32 form as the only option for inc eax.)

Upvotes: 2

zargothrax
zargothrax

Reputation: 27

The opcode refers to the binary sequence that identifies the instruction. So for the 8085 I believe 0x80 would be the opcode for "ADD B"

A mnemonic is a human readable name that helps you remember the instructions. So the string "ADD B" is a mnemonic for 0x80. "ADD B" is a lot easier to remember than 0x80.

Upvotes: 2

SergeyA
SergeyA

Reputation: 62583

Usually opcode refers to the type of operation (ADD), and register B is an operand. However, with a fixed and small number of operands, the same operation can have different opcode for all possible operands.

Upvotes: 2

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