Makefile called in target

Question

I have a makefile, called "Makefile", and some target in it like:

file.o: file.c Makefile
      gcc <some flags & options> file.c

What exactly does file.o: file.c Makefile do?

Answer 1

That line describes the dependencies for file.o.

If any file listed after the : (file.c and Makefile in this case) has been modified later than file.o, then file.o is rebuilt according to the command in the following line.