CODEWITHSUNDEEP
verilogsystem-verilogxilinxiverilog
andrsmllr
andrsmllr

Reputation: 1223

Declaration of a Verilog function in a header file

When I try to compile a testbench which includes a header file which contains a function declaration Icarus Verilog (v10.0 stable) aborts with the following error: 

mpeg.vh:133: error: function declarations must be contained within a module.

This error is quite clear. However, the header file is in fact included inside of a module (the testbench). Since an include directive should just be replaced by the text inside the respective header file the function declaration is in fact contained within a module (contrary to what the error message claims). I have used this header file before with Xilinx ISE (fuse/isim) which worked just as intended. There wasn't even a warning.

Is it allowed to declare a function inside a header file (for later inclusion inside of a module)?

I was unable to find the answer to this question in the Verilog LRM (IEEE 1364-2001, Chapter 10).

Example:

test.vh:

function integer foo;
  input integer a;
begin
  foo = a;
end
endfunction

test.v:

module bar;
`include "test.vh"
endmodule

Call iverilog: iverilog -o test.o -Wall test.v test.vh

Upvotes: 1

Views: 4398

Answers (1)

dave_59
dave_59

Reputation: 42698

In the old Verilog standard, nothing is allowed outside the scope of a module/endmodule pair. Compiler directives (things that start with `) are an exception because they are pre-processed before any other syntax.

SystemVerilog added the concept of a compilation unit, which allows code to exist outside the scope a module. But it also added packages that can be imported instead of `included to get rid of the problem of having a function multiply defined when you what one of them.

Upvotes: 2

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