How to create makefile specifying ifferent directories for object and executable files

Question

    --folder
    ----book.h
    ----book.cpp
    ----library.h
    ----library.cpp
    ----main.cpp

this is the directory structure and I have created this make file which generate object files and executable files in the same directory.

    main : main.o book.o library.o
        g++ main.o book.o library.o -o main

    main.o : main.cpp book.h library.h
        g++ -c main.cpp

    library.o : library.cpp library.h book.h
        g++ -c library.cpp

    book.o : book.cpp book.h 
        g++ -c book.cpp

    clean:
        rm -f *.o main

But i want to create folders obj and bin respectively for object files and executable files in the folder. How can I do it?

Answer 1

You can just prefix your objects with obj/ and your executable with bin/ and add a command to make the directories mkdir -p bin etc..

# make your subfolders targets
all: bin obj bin/main

bin/main : obj/main.o obj/book.o obj/library.o
    g++ -o bin/main obj/main.o obj/book.o obj/library.o

obj/main.o : main.cpp book.h library.h
    g++ -c -o obj/main.o main.cpp

obj/library.o : library.cpp library.h book.h
    g++ -c -o obj/library.o library.cpp

obj/book.o : book.cpp book.h 
    g++ -c -o obj/book.o book.cpp

# create subfolders if not present
bin obj:
    mkdir -p bin
    mkdir -p obj

clean:
    rm -f bin/* obj/*

Then just type make (makes targer all).

Answer 2

Maybe something like this

TARGET  = bin/main
SOURCES = main.cpp book.cpp library.cpp
OBJ_DIR = obj

OBJECTS = $(SOURCES:%.cpp=$(OBJ_DIR)/*.o)

$(TARGET): $(OBJECTS)
    $(LD) $(LDFLAGS) $^ -o $@ $(LIBS)

$(OBJ_DIR)/%.o: %.cpp
    $(CXX) $(CXXFLAGS) $< -c -o $@

This requires that the bin and obj directories exist first.

Read the GNU Make manual for more information.

---

I had some time over so I wrote up a complete and automated Makefile for you. This will create the directories if they do not exist.

BINDIR  = bin/
OBJDIR  = obj/

TARGET  = $(BINDIR)target
SOURCES = main.cpp book.cpp library.cpp

LD      = g++

OBJECTS = $(SOURCES:%.cpp=$(OBJDIR)%.o)

.PHONY: all
all: target

.PHONY: target
target: before_target actual_target after_target

.PHONY: before_target
before_target: $(OBJDIR) $(BINDIR)

.PHONY: actual_target
actual_target: $(TARGET)

.PHONY: after_target
after_target:

$(TARGET): $(OBJECTS)
    $(LD) $(LDFLAGS) $^ -o $@ $(LIBS)

$(OBJDIR)%.o: %.cpp
    $(CXX) $(CXXFLAGS) $^ -c -o $@

$(OBJDIR) $(BINDIR):
    mkdir $@

.PHONY: clean
clean:
    -rm -rf $(BINDIR)
    -rm -rf $(OBJDIR)

Answer 3

Use VPATH! Here is an article that does an excellent (and detailed) job of showing you how: Multi-Architecture Builds.

And here is the basic theory:

First, there will be a single level of recursion. This will be to handle automatically cding into the object directory, not for any directory-hierarchy reason.

Second, you will use VPATH to specify the location of the source code relative to the object directory: VPATH=../src

Third ... um ... profit!

Here's a simplified example (not tested). You can expand this, or follow along with the article to get a "richer" version:

ifneq (obj,$(notdir $(CURDIR)))
    # Not in object directory, so we must be in root (src) directory!

    .SUFFIXES:

    OBJDIR := obj

    MAKETARGET = $(MAKE) --no-print-directory -C $@ -f $(CURDIR)/Makefile \
             SRCDIR=$(CURDIR) $(MAKECMDGOALS)

    .PHONY: $(OBJDIR)
    $(OBJDIR):
        ;+@[ -d $@ ] || mkdir -p $@
        +@$(MAKETARGET)

    Makefile : ;
    %.mk :: ;

    % :: $(OBJDIR) ; :

    .PHONY: clean
    clean:
        rm -rf $(OBJDIR)
else
    VPATH=../src
    CXX := g++  # The default, just so you know it's here

    # CXXFLAGS = ...
    # LDFLAGS = ...
    # LDLIBS = ...

    main : main.o book.o library.o

    main.o : main.cpp book.h library.h

    library.o : library.cpp library.h book.h

    book.o : book.cpp book.h 

endif