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fpgamultiplicationsynthesisquartus
hooray9
hooray9

Reputation: 153

How to use Quartus to optimize combinational logic?

I am using Quartus to synthesize a combinational circuit to FPGA. Right now I want to get the best possible maximum frequency without considering the resource consumption. The current critical path is composed by a sequence of multiplications like this:

res = a * b * c *d

I am wondering whether it is possible for Quartus to automatically generate an equivalent combinational logic that has shorter critical path like this:

ab  = a * b
cd  = c * d
res = ab * cd

Which have only two multipliers on the critical path. I found an online document from Quartus mentioned that this is possible but without instructions on how to do it:UsingTimeQuestAnalyzer

Pipelining doesn't work here since I don't want to change the timing of this combinational circuitry.

Upvotes: 0

Views: 903

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

A synthesis tool like Quartus usually builds the initial internal structure based on the HDL (VHDL/Verilog) code, and then reorganize and optimizes that structure depending on constrains and area, to the extend that the tool has rules for manipulating the structures. Finally the tool does the timing check to see that timing is adhered to for the resulting design.

For implementation of the multiplication * operator, it appears as Quartus simply implements a * b * c * d using the left associative property of *, thus as ((a * b) * c) * d, and does not apply the associative rule to make (a * b) * (c * d) in order to meet the timing requirements.

So if you want to make the multiplier like:

res = (a * b) * (c * d)

you can help the synthesis tool writing HDL as (VHDL used):

ab <= a * b;
cd <= c * d;
res <= ab * cd;

And remember to make timing constrains that matches the requirements, to check that the resulting implementation meets the required timing. Path requirements can be made like, for a to res with maximum of 12 ns delay:

set_max_delay -from [get_ports a[*]] -to [get_ports res[*]] 12
...

The RTL and technology structure is then as in this figure:

enter image description here

Where a expression like res = a * b * c * d gives this structure:

enter image description here

And timing follows the implementation as expected.

So you can often control the implementation through the structure of the HDL code, if the structure you advise by the HDL code will meet timing, and the synthesis tool can't optimize this further for area while still meeting the timing requirements.

Upvotes: 1

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