CODEWITHSUNDEEP
cmakefile
marmistrz
marmistrz

Reputation: 6392

`make` without manual Makefile writing

I'll have two write a project or two in plain C this year. To automate the compilation (besides, I'd like to use the build plugin for Atom) I'd like to have a Makefile.

But I'm not really fond of specifying all the commands manually. I'd rather specify the source files and headers (in the correct order) and let the program build the rest for me.

Is there any tool that I could use? Or should I reconsider writing the Makefiles manually?

Upvotes: 2

Views: 822

Answers (2)

Frederik Hartmann
Frederik Hartmann

Reputation: 41

This should be seen as an addition to Joachims answer on how to string it all together.

I have a makefile that I use for more or less everything, that has automatic dependency discovery and automatic source file discovery. While is might not be the right fit for large projects, I find it extremly convinient for small prototypes and programs.

I have collected and commented the importent parts here:

CC:=gcc                 # Define the Compiler
CFLAGS:=-O2 -g          # Define the Compiler Options
SRC_DIR:=src            # Source is in this folder
BIN_DIR:=bin            # objects will be places in this folder

# Discover all C files
SRC:=$(shell find $(SRC_DIR) -type f -name *.c)
# Every C file is compiled into one object file
OBJ:=$(addprefix bin/,$(notdir $(patsubst %.c,%.o,$(C_SRC))))
# Every C file creates a dependency file
DEP:=$(patsubst %.c,%.d,$(C_SRC)

# Include the dependencies
-include $(DEP)

all: executable

# Bind all objects into the executable
executable: $(OBJ)
        $(CC) $^ -o executable

# Recipe to create the dependencie files from the source files
.d: %.c
        $(CC) -MM -MT"$(BIN_DIR)/$(notdir $(<:.c=.o))" -MF "$@" "$<"

# Recipe to do the compilation
$(C_OBJ):bin/%.o:
        -$(STYLEC) $^
        $(CC) $(CFLAGS) -c -o $@ $<

This will take all source files from the src/ folder, generate the dependencies with the gcc and then do the correct compilation/binding.

Upvotes: 2

Some programmer dude
Some programmer dude

Reputation: 409176

make have many implicit rules that will create object files from C source file without you writing any commands. All you really need to do is list the object files needed for the program.

For example, lets say you have to source files, a.c and b.c, and you want to create the program p., then all you need is

p : a.o b.o
    $(CC) $^ -o $@

$(CC) is the variable used for the C compiler frontend program, which is also used to link. make creates this for you and it's usually cc.

$^ is a list of all per-requisites for the rule, in this case a.o b.o.

$@ is the name of the target of the rule, in this case p.

Using this very simple makefile, make will compile the C sources to object files, and then with the provided rule link the object files into an executable program.

From the above makefile you can start customizing, for example tell make to explicitly use gcc instead of cc by setting the CC variable. Or set special compiler flags by creating and setting the CFLAGS variable. Adding targets to "clean" (usually remove the program and the object files). And much much more.

I suggest you learn about make and makefiles, and for this you should read the GNU make online manual, before going on to other build systems.

The GNU build system is still very common, but it have been losing ground lately, mostly to CMake (which I personally favor) but there are many other build systems out there. Some (like CMake) can be used to generate makefiles, while others are straight replacements for make.

Upvotes: 5

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