CODEWITHSUNDEEP
cachingmemory-managementoperating-system
Hiren
Hiren

Reputation: 77

Does data pass through cache(L3,L2,L1) from RAM before processing it?

I have been reading about cache memory and I found an interesting answer from Quora here

Cache memory (L1,L2,L3)

But here I am a bit confused with if CPU wants to process data from RAM so does it pass through like:

CPU <- Register <- L1 <- L2 <- L3 <- RAM

Or the instruction directly passes to registers via Memory bus?

Upvotes: 5

Views: 2171

Answers (1)

Hadi Brais
Hadi Brais

Reputation: 23639

The definition of a cache is that it's a memory structure that has a lower latency (faster) than the memory below it. Beyond this, you can design a cache system any way you want. For example, when loading a data block from main memory, it can be loaded into all levels of the cache hierarchy and then the requested part of that block is loaded into a register. The exact details depend on the microarchitecture. In addition, the instruction cache and the data cache can have different policies.

Upvotes: 5

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