CODEWITHSUNDEEP
verilog
Harsha
Harsha

Reputation: 47

"Illegal output or inout port connection for "port"

I have coded a small code for two point FFT, where my inputs ( 64-bit complex) are in IEEE-754 format(double precision). Here is the link for my codes (butterfly module, adder/subtractor module, testbench):

http://pastebin.com/RNRx6J2E

when I try simulating the testbench I am facing the following list of errors:

http://pastebin.com/LRnRzv4A

P.S : I am beginner, so, my style of writing may be bad. Please help me solving this issue.

Upvotes: 3

Views: 12054

Answers (1)

sharvil111
sharvil111

Reputation: 4381

Referring to this link provided in comment by OP. Your code works fine with all SystemVerilog simulators. The output of module must be connected to a wire. Refer the following figure:

Port connection rules

The output port from inside the module can be a reg or wire. But, when that module is instantiated, it must be connected to a net or wire.

Referring to IEEE 1800-2012, Section 23.3.3:

Each port connection shall be a continuous assignment of source to sink, where one connected item shall be a signal source and the other shall be a signal sink. The assignment shall be a continuous assignment from source to sink for input or output ports.

When the ports are connected in an instantiation, to any other port, it is a constant assignment, and hence it always requires the target port to be a net.

So, in this code, connect wires to the output module add_sub and assign the values of wires to the reg outr1,outr2 etc.

  // Draw wires to be connected as output
  wire [63:0] t1,t2,ti1,ti2;

  // Drive all regs from values of wires
  always @*
    begin
      outr1 = t1;
      outr2 = t2;
      outi1 = ti1;
      outi2 = ti2;
    end

  // Change : Wires connection
  add_sub adder1(en,clk,inr1[63],inr2[63],inr1[62:52],inr2[62:52],inr1[51:0],inr2[51:0],1'b0,t1[63],t1[62:52],t1[51:0]);
  //...

I have simulated your code with all simulators at EDAPlayground here and it works fine. Refer to this and this similar questions.

Upvotes: 4

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