CODEWITHSUNDEEP
arraysverilogfpgamodelsim
Tony
Tony

Reputation: 23

Verilog Array Assignment

So I am trying to assign numbers to an array in verilog, and it goes like this:

initial begin

waveforms[0] = 16'b1100100100000000;
waveforms[1] = 16'b1000000000000000;
waveforms[2] = 16'b1111111111111111;

end

And the following codes can pass ModelSim Compiler. However, I have a huge lookup table need to store in this "waveforms", so apparently assign the value one by one is not efficient. So I tried this:

initial begin

 waveforms [0:2] = '{16'b1100100100000000,16'b1000000000000000,16'b1111111111111111};

end

And, by doing the above, I get the following error:

(vlog-2110) Illegal reference to memory "waveforms".

Illegal array access into "waveforms"

Illegal LHS of assignment.

So, question is how to fix these errors?

Thanks

Upvotes: 2

Views: 2737

Answers (1)

dave_59
dave_59

Reputation: 42616

Only SystemVerilog allows you to assign arrays as an aggregate. Change the file extension from *.v to *.sv

Another option is to use $readmemb and load the lookup table from another file.

Upvotes: 2

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