4-Bit Johnson Counter in VHDL

Question

I am working on implementing a 4-bit Johnson counter on an Altera DE2 board in VHDL for my logic design lab. The code compiles as it is written, but when I program it onto the board nothing happens. My lab partner and I cannot figure it out and neither can the TA so any help from someone with more knowledge of VHDL than I would be greatly appreciated!! Heres the code...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity lab7 is
port ( 
    LEDG : out bit_vector(3 downto 0);
    SW: in bit_vector(3 downto 0) 
      );
end lab7;

architecture LogicFunc of lab7 is
signal Q0 : bit;
signal Q1 : bit;
signal Q2 : bit;
signal Q3 : bit;
signal K  : bit;

component flipflop 
port(D,Clock : in bit;
    Q: out bit);
end component;

begin
K <= SW(3);
flipflop1: flipflop port map(Q3, K, Q0);
flipflop2: flipflop port map(Q0, K, Q1);
flipflop3: flipflop port map(Q1, K, Q2);
flipflop4: flipflop port map(Q2, K, Q3);
end;

-- D flipflop 
entity flipflop is
port(D     : in bit;
     Clock : in bit;
     Q     : out bit);
end flipflop;

architecture behavior of flipflop is    
begin
    process(Clock)
    begin
     if Clock'event and Clock = '1' then
           Q <= D;
     end if;
    end process;
end behavior;

--port map: D, Clock, Q

Answer 1

There are two things wrong (without approaching whether SW(3) is debounced).

First LEDG isn't connected to the Q outputs of the four flipflops and second the Johnson counter doesn't contain a '1'.

Both of these are addressed here:

-- D flipflop 
entity flipflop is
port(D     : in bit;
     Clock : in bit;
     Q     : out bit);
end flipflop;

architecture behavior of flipflop is    
begin
    process(Clock)
    begin
     if Clock'event and Clock = '1' then
           Q <= D;
     end if;
    end process;
end behavior;

-- library IEEE;
-- use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.NUMERIC_STD.ALL;

entity lab7 is
port ( 
    LEDG : out bit_vector(3 downto 0);
    SW: in bit_vector(3 downto 0) 
      );
end lab7;

architecture LogicFunc of lab7 is
signal Q0 : bit;
signal Q1 : bit;
signal Q2 : bit;
signal Q3 : bit;
signal K  : bit;
signal I:   bit;

component flipflop 
port(D,Clock : in bit;
    Q: out bit);
end component;

begin
K <= SW(3);
flipflop1: flipflop port map( I, K, Q0); -- was (Q3, ..)
flipflop2: flipflop port map(Q0, K, Q1);
flipflop3: flipflop port map(Q1, K, Q2);
flipflop4: flipflop port map(Q2, K, Q3);

    LEDG <= (Q3,Q2,Q1,Q0); -- added 
    I <= (not Q0 and not Q1 and not Q2 and not Q3) or Q3; -- added
end;

-- D flipflop 
entity flipflop is
port(D     : in bit;
     Clock : in bit;
     Q     : out bit);
end flipflop;

architecture behavior of flipflop is    
begin
    process(Clock)
    begin
     if Clock'event and Clock = '1' then
           Q <= D;
     end if;
    end process;
end behavior;
--port map: D, Clock, Q

entity lab7_tb is
end entity;

architecture foo of lab7_tb is
    signal LEDG: bit_vector (3 downto 0);
    signal SW:   bit_vector (3 downto 0);
begin
DUT:
    entity work.lab7
        port map (
            LEDG => LEDG,
            SW => SW
        );
STIMULUS:
    process
    begin
        wait for 1 sec;
        SW(3) <= not sw(3);
        if now > 30 sec then
            wait;
        end if;
    end process;
end architecture;

I added a testbench which shows the johnson counter in simulation:

Note without added a set input to the flip flops I used an AND gate detecting a state (all '0s) and an OR gate to feed that in to the D input of flipflop1 as well as the output of flipflop4. This assumed you were intending an Overbeck ring counter (hooking up Q3 to flipflop1's D input).

There's also an added assignment to LEDG from the individual flipflops Q outputs.

Because you your question mentions Johnson you can modify the value of I:

    LEDG <= (Q3,Q2,Q1,Q0); -- added
    I <= not Q3; --added
    -- I <= (not Q0 and not Q1 and not Q2 and not Q3) or Q3; -- added

And create a true Johnson counter that produces gray code: