CODEWITHSUNDEEP
vhdl
user6345302
user6345302

Reputation:

VHDL can't determine definition of operator "+"

When I am trying to compile my code it has an error in the following part:

overflow <= input_a(15) + input_b(15);

I had declared the input_a and input_b as 15 bit vectors and the libraries that I am using are : 

library ieee; 
use ieee.std_logic_1164.all;

So the error is :

Error (10327): VHDL error at alu16.vhd(45): can't determine definition of operator ""+"" -- found 0 possible definitions

Thanks in advance

Upvotes: 1

Views: 24274

Answers (4)

guigenta
guigenta

Reputation: 21

Try including the unsigned library...it worked for me! I have the libraries listed and I could did the sum

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Upvotes: 2

A. Kieffer
A. Kieffer

Reputation: 372

If you want to perform arithmetic operations you should declare signed/unsigned signals instead of bit_vector/std_logic_vector.

Those last types can only be used with logical operations such as and/or ... because the compiler doesn't know whether you want your signal to be signed or unsigned.

When using signed/unsigned types you have to use the IEEE numeric_std package.

Upvotes: 1

Alscylla
Alscylla

Reputation: 1

Add this : use ieee.std_logic_unsigned.all; so you can use the operations + - ... with std_logic

Upvotes: -1

Morten Zilmer
Morten Zilmer

Reputation: 15924

If input_a and input_b are std_logic_vector, then input_a(15) and input_b(15) are std_logic, but VHDL does not have a + operator defined for std_logic, thus the error.

If you want to generate a result based on two std_logic values, you have the standard logical operators as and, or, xor, and not available, which will suffice.

Upvotes: 5

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