CODEWITHSUNDEEP
c++makefile
PabloMon
PabloMon

Reputation: 41

Make recompiles non modified files

I have a makefile for my program but I got everything recompiled every time I run it, even if I modify nothing. Every time I run make it recompiles simHwIntf.cpp showHelp.cpp and sendFromFile.cpp

This is my make file:

IDIR    = inc
LDIR    = -L/usr/lib/x86_64-linux-gnu/
SDIR    = src
ODIR    = obj
BINDIR  = bin
LDLIBS  = -luhd
OBJ     = $(patsubst %,$(ODIR)/%,$(O_FILES))

CC      = g++
CFLAGS  = -Wall -std=c++11 -I $(IDIR) #-Werror

BINARIES= main

C_FILES = simHwIntf.cpp showHelp.cpp  sendFromFile.cpp
H_FILES = simHwIntf.h
O_FILES = $(C_FILES:.cpp=.o)

all: $(BINARIES)
@echo "Make file executed"

$(BINARIES): $(O_FILES)
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(OBJ) $(LDIR) $(LDLIBS) 

fileCreator: fileCreator.o 
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(ODIR)/fileCreator.o

fileHandler: fileHandler.o
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(ODIR)/fileHandler.o

backYard: backYard.o
$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(ODIR)/backYard.o

%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
$(CC) $(CFLAGS) -c -o $(ODIR)/$@ $<

clean: 
-rm -rf $(ODIR)/*.o *~

distclean: clean
-rm -rf $(BINDIR)/*

Each time the output in the shell is:

g++ -Wall -std=c++11 -I inc  -c -o obj/simHwIntf.o src/simHwIntf.cpp
g++ -Wall -std=c++11 -I inc  -c -o obj/showHelp.o src/showHelp.cpp
g++ -Wall -std=c++11 -I inc  -c -o obj/sendFromFile.o src/sendFromFile.cpp
g++ -Wall -std=c++11 -I inc  -o bin/main obj/simHwIntf.o obj/showHelp.o obj/sendFromFile.o -L/usr/lib/x86_64-linux-gnu/ -luhd 
Make file executed

I've already search and read this: (How do I make Makefile to recompile only changed files?) but didn't help much.

Anybody that could give me a hand with this ?

I have a doubt with the directories, maybe one or several directories are re-created each time I run make and this causes everything inside to look like new to the compiler.

Thanks

Upvotes: 4

Views: 277

Answers (3)

encoctmebreu
encoctmebreu

Reputation: 1

Directories matter when you define targets.

If a define a rule

myexec: objdir/myexec.o
    $(CC) $(CFLAGS) -o bindir/myexec objdir/myexec.o $(LDFLAGS)

Make believes that that this would create the file myexec in the working directory. When you rerun make the target myexec wasn't found, so it will be created again. Add the paths in the targets and it should work.

Try replacing

BINARIES= main

with

BINARIES= $(BINDIR)/main

and the rule

$(CC) $(CFLAGS) -o $(BINDIR)/$@ $(OBJ) $(LDIR) $(LDLIBS)

with

$(CC) $(CFLAGS) -o $@ $^ $(LDIR) $(LDLIBS)

And change the other rules similarly.

Note, in general it is a bad idea to use $@ in combination with a path when creating the target in some rule (as in $(BINDIR)/$@), because this will never create the actual target file. A bare $@ should be sufficient.

Upvotes: 0

Tim
Tim

Reputation: 1933

You can see what triggered the build by echoing the dependencies that changed. Add this to your %.o target : 

@echo [triggered by changes in $?]

You should also use the VPATH special variable instead of specifying the sources path in your %.o target. See GNU make VPATH documentation

Upvotes: 6

GMichael
GMichael

Reputation: 2776

Please try replacing 

%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
     $(CC) $(CFLAGS) -c -o $(ODIR)/$@ $<

with

$(ODIR)/%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
     $(CC) $(CFLAGS) -c -o $(ODIR)/$@ $<

Upvotes: 3

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